Bit Shift Overflow

Overview

The bit shift overflow detector identifies SHL, SHR, and SAR operations where the shift amount is derived from user input or exceeds the operand’s bit width. In the EVM, shifting a 256-bit value by 256 or more bits produces zero — if this zeroed value is used in a division denominator, price calculation, or balance check, the result is a critical math error.

The Cetus DEX exploit ($223M, May 2025) exploited an unsafe bit shift in a concentrated liquidity calculation, where a shift amount derived from tick math overflowed, zeroing a critical intermediate value.

Why This Is an Issue

Bit shifts are often used in fixed-point math libraries, tick-to-price conversions in concentrated liquidity AMMs, and fee calculations. When the shift amount is unchecked, an attacker can provide an input that causes a shift of 256+ bits, zeroing the result. If that result is used as a divisor or a price, the consequences range from division by zero to massive over/under-pricing.

How to Resolve

// Before: Vulnerable — unchecked shift amount
function tickToPrice(int24 tick) public pure returns (uint256) {
    uint256 absTick = uint256(int256(tick < 0 ? -tick : tick));
    uint256 ratio = absTick & 0x1 != 0 ? 0xfff97272 : 1 << 128;
    ratio >>= absTick;  // If absTick >= 256, ratio becomes 0
    return ratio;
}

// After: Fixed — validate shift amount
function tickToPrice(int24 tick) public pure returns (uint256) {
    uint256 absTick = uint256(int256(tick < 0 ? -tick : tick));
    require(absTick < 256, "Tick out of range");
    uint256 ratio = absTick & 0x1 != 0 ? 0xfff97272 : 1 << 128;
    ratio >>= absTick;
    return ratio;
}

Detection Methodology

1. Shift instruction identification: Locates SHL, SHR, and SAR opcodes.
2. Shift amount tracing: Traces the shift amount operand to determine if it originates from user input or an unchecked computation.
3. Bounds check detection: Searches for comparisons ensuring the shift amount is less than 256 before the shift.
4. Result usage analysis: Higher confidence when the shift result flows into division, comparison, or transfer operations.

Limitations

False positives: Fixed shift amounts used in constant expressions may be flagged if the detector cannot resolve the constant. False negatives: Shift amounts computed through complex multi-step arithmetic may not be fully traced.

Related Detectors

• Integer Overflow — detects overflow in arithmetic operations
• Precision Errors — detects precision loss in calculations

References

• EVM Opcodes — SHL, SHR, SAR
• CWE-190: Integer Overflow or Wraparound